The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of transmitting data at read and write operations at a high speed.
Generally, in a system having a plurality of semiconductor devices, a semiconductor memory device is provided to store data. When data are requested from a data processing apparatus such as a CPU, the semiconductor memory device outputs the data which are correspondent to address signals from an external circuit or stores the data to memory cells which are correspondent to address signals.
As the system which is implemented by a plurality of the semiconductor devices increases its operating speed and the semiconductor integration has been gradually developed, the semiconductor memory device has increased its demand for a high-speed data processing mechanism. In order that the semiconductor memory device stably and quickly operates, various circuits within the semiconductor memory device also operate in a high speed and the signal transmission between the circuits is also performed at a high speed.
Actually, in the semiconductor memory device, the data processing can be delayed by a plurality of control circuits to read out the data from a unit cell and transmit input data from the external circuit to the unit cell and a transmission line and a connecting apparatus to transfer the data. Also, a delay is caused when the data from the semiconductor memory device are transferred to an apparatus of the system to request the data. In the high-speed system, the delay time required to transfer the signal and data functions as a factor to deteriorate the system performance and reduce the reliability of the whole operation of the system. The delay caused on the data transmission path has a possibility of a change based on a given operating environment and this has a bad effect on the operation of the semiconductor memory device.
Generally, the more an output operation to output the data from a unit cell (read operation) is processed at a high speed after a command is inputted from an external circuit, the more the operating performance of the semiconductor memory device improves. In case of a semiconductor memory device for a graphic data process in which a large amount of data such as an image data are processed, the data output timing is used as an important factor to evaluate the memory device performance. Further, the stability of the system can be guaranteed when the output data from the semiconductor memory device are transmitted exactly to various data processing units.
FIG. 1 is a timing chart illustrating a read operation of a conventional semiconductor memory device. In FIG. 1, a data transmission is illustrated between a semiconductor memory device and a graphic processing unit (GPU) for the graphic data.
As shown in FIG. 1, a DDR (DOUBLE DATA RATE) semiconductor memory device (DDR SDRAM) outputs DRAM data in synchronization with a rising edge signal and a falling edge signal of a memory clock signal in a read operation which is requested from a graphic processing unit. Also, the graphic processing unit receives the data in synchronization with the rising edge signal and the falling edge signal of a graphic clock signal. At this time, the graphic processing unit exactly receives the data (GPU DATA) when the rising and falling edges are positioned within a data valid window of the data outputted from DDR SDRAM.
A delay time of t2−t1 is caused by a physical phenomenon which exists on the data transmission between the semiconductor memory device and the graphic processing unit. Although the data are outputted in synchronization with the edges of the clock signal in the semiconductor memory device, the graphic processing unit exactly transfers the transmitted data when the edges are positioned within the data valid window, preferably in the middle of the data valid window. Accordingly, a phase difference of 0.5*UI (UI is a data valid window) between the memory clock (DRAM clock) and the graphic clock (GPU clock) is adequate to meet the ideal condition and the data delay time can be considered to be approximately t2−t1+0.5*UI based on physical factors which exist between the semiconductor memory device and the graphic processing unit. As a result, as shown in FIG. 1, the operations of the semiconductor memory device and the graphic processing unit are carried out based on the different phase. The different clock operation between the semiconductor memory device and the graphic processing unit means that there is a presence of a mismatch between a data transmission clock and a data acknowledgement clock (i.e., data trigger signal).
To obtain a stable operation against this mismatch, the semiconductor memory device or the system having such a semiconductor memory device predetermines the delay time between the semiconductor memory device and the graphic processing unit. Accordingly, an additional clock signal such as a read strobe signal RDQS and a write strobe signal WDQS is employed or an additional specification, such as an output access time tAC, a data strobe signal output access time output tDQSCK or a data strobe signal to data output time tDQSQ, is employed in the semiconductor memory device.
However, since the specification of the semiconductor memory device is physically prescribed by a constant value between the semiconductor memory device and the graphic processing unit, it is difficult to guarantee a normal data transmission in the actually implemented system. Particularly, since the data are increased on a channel between the semiconductor memory device and the graphic processing unit in a high-speed system, the stable data transmission is much more difficult.
To overcome the above-mentioned problem, the recent semiconductor memory device and graphic processing unit are provided to cope with the high-speed data transmission through a data training. The data training is a technique to control a skew between the data by using a data pattern which is prescribed between a controller and the semiconductor memory device in order to stably transmit the data at the read and write operations. For instance, in the specification of DDRIII semiconductor memory device, a write leveling technique is employed to compensate for the time difference which is caused by a delay between a clock signal HCLK and a data strobe signal DQS. The data strobe signal is produced by programmable delay elements which can satisfy a timing requirement, including tDQSS, tDSS and tDSH of the semiconductor memory device, by compensating for the skew between the data strobe signal and the clock signal through the write leveling technique.
Graphic memory devices, which are recently introduced, are designed to transmit the data over 4 Gbps and the specification prescribes the data training in the graphic memory device in order to meet this high-speed operation.